As known, sampling circuits are applied to many circuitry systems. FIG. 1 schematically illustrates a conventional analog-to-digital conversion system. As shown in FIG. 1, the analog-to-digital conversion system 100 comprises a buffering circuit 110 and an analog-to-digital converter (ADC) 120.
The buffering circuit 110 is a differential buffering circuit. Moreover, the buffering circuit 110 generates a differential signal pair (vip, vin) to two input terminals of the analog-to-digital converter 120. The signals vip and vin of the differential signal pair are complementary analog signals. The amplitudes of the signals vip and vin are equal. Moreover, the signals vip and vin have different signs. For example, in case that the first signal vip is +1, the second signal vin is −1.
The analog-to-digital converter 120 comprises a differential sampling circuit 122. The differential sampling circuit 122 comprises switching elements sw1, sw2 and sampling capacitors Ca1, Cb1. The capacitance values of the sampling capacitors Ca1 and Cb1 are equal.
A first terminal of the switching element sw1 is connected with a first input terminal of the analog-to-digital converter 120 so as to receive the first signal vip of the differential signal pair. The sampling capacitor Ca1 is connected between a second terminal of the switching element sw1 and a ground terminal. A first terminal of the switching element sw2 is connected with a second input terminal of the analog-to-digital converter 120 so as to receive the second signal vin of the differential signal pair. The sampling capacitor Cb1 is connected between a second terminal of the switching element sw2 and the ground terminal.
FIG. 2A schematically illustrates the operations of the differential sampling circuit of FIG. 1 during a sampling cycle. FIG. 2B schematically illustrates the operations of the differential sampling circuit of FIG. 1 during a holding cycle. The sampling cycle and the holding cycle are alternate cycles.
During the sampling cycle, the switching elements sw1 and sw2 are in a close state. Meanwhile, the two input terminals of the analog-to-digital converter 120 are connected with the sampling capacitors Ca1 and Cb1, respectively. Consequently, the voltage +v1 of the first signal vp1 and the voltage −v1 of the second signal vin are stored in the sampling capacitors Ca1 and Cb1, respectively.
During the holding cycle, the switching elements sw1 and sw2 are in an open state. Meanwhile, the two input terminals of the analog-to-digital converter 120 are disconnected from the sampling capacitors Ca1 and Cb1. Meanwhile, the voltages +v1 and −v1 are still stored in the sampling capacitors Ca1 and Cb1, respectively. According to the stored voltages of the sampling capacitors Ca1 and Cb1, a processing circuit of the analog-to-digital converter 120 acquires a difference voltage Δv between the voltages +v1 and −v1. The difference voltage Δv is 2v1, i.e., v1−(−v1)=2v1.
According to the difference voltage Δv, the processing circuit calculates a digital code. The digital code is used as an output digital code of the analog-to-digital converter 120.